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Integrated Circuits Inc.
APLUS
aP89021/010
MAKE YOUR PRODUCTION A-PLUS
VOICE OTP IC aP89021 - 21sec AP89010 - 10sec
APLUS
INTEGRATED CIRCUITS INC.
Sales E-mail:
Address: 3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei, Taiwan 115, R.O.C. (115) 32 3 10. TEL: 886-2-2782-9266 FAX: 886-2-2782-9255 WEBSITE : http: //www.aplusinc.com.tw
sales@aplusinc.com.tw
Technology E-mail:
service@aplusinc.com.tw
Ver 2.2
1
May 31, 2007
Integrated Circuits Inc.
FEATURES
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aP89021/010
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Standard CMOS process. Embedded 512K/256K bits EPROM. 21/10 Sec Voice Length at 6 KHz sampling and 4-bit ADPCM compression. Maximum 12 voice groups. Combination of voice building blocks to extend playback duration. 960 table entries are available for voice block combinations. User selectable PCM or ADPCM data compress. Two triggering modes are available by whole chip option during voice compilation. - Key Trigger Mode - Combinations of S1 ~ S4 to trigger up to 12 voice groups; SBT for sequential trigger. - CPU Parallel Trigger Mode - Combinations of S1 ~S4 with SBT goes HIGH to strobe start the voice playback. Voice Group Trigger Options: Edge / Level; Hold / Un-hold; Retrigger / Non-retrigger. Whole Chip Options: Ramp / No-ramp; Output Options; Key / CPU trigger mode. 16ms (@ 8KHz sampling rate) Debounce Time for both Key and CPU Trigger Modes. RST pin set to HIGH to stop playback at once. Three user programmable outputs for STOP plus, BUSY signal and flashing LED. Built-in oscillator to control sampling frequency with an external resistor. 2.2V - 3.6V single power supply and < 5uA low stand-by current. PWM Vout1 and Vout2 drive speaker directly. D/A COUT to drive speaker through an external BJT. Development System support voice compilation and options selection.
DESCRIPTION
aP89021/010 high performance Voice OTP is fabricated with Standard CMOS process with embedded 512K/256K bits EPROM. It can store up to 21/10 sec voice message with 4-bit ADPCM compression at 6KHz sampling rate. 8-bit PCM is also available as user selectable option. Two trigger modes, simple Key trigger mode and Parallel CPU trigger mode facilitate different user interface. User selectable triggering and output signal options provide maximum flexibility to various applications. Built-in resistor controlled oscillator, 8-bit current mode D/A output and PWM direct speaker driving output minimize the number of external components. PC controlled programmer and developing software are available.
Ver 2.2
2
May 31, 2007
Integrated Circuits Inc.
PIN CONFIGURATIONS
aP89021/010
OUT1 VOUT1 VOUT2 VSS OUT2 OUT3 COUT OSC
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
RST SBT S4 S3 VDD S2 S1 VPP
300 mil DIP 150 mil SOP
PIN NAMES
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Playback Mode OUT1 VOUT1 VOUT2 VSS OUT2 OUT3 COUT OSC VPP S1 S2 VDD S3 S4 SBT RST OTP Program Mode OEB VSS IO ACLK VPP S1 S2 VDD S3 S4 PGM DCLK Description Programmable output (I/O pin) PWM output to drive speaker directly PWM output to drive speaker directly Power Ground Programmable output (I/O pin) Programmable output (I/O pin) D/A current output Oscillator input Supply voltage for OTP programming Trigger pin (input with internal pull-down) Trigger pin (input with internal pull-down) Positive Power Supply Trigger (input with internal pull-down) Trigger (input with internal pull-down) Trigger pin (input with internal pull-down) Reset pin (input with internal pull-down)
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Integrated Circuits Inc.
PIN DESCRIPTIONS
S1 ~ S4
aP89021/010
Input Trigger Pins: - S1 to S4 are used to trigger the 12 Voice Groups in both Key and CPU Parallel Trigger Mode. - In OTP Programming Mode, S1 to S4 are used as program enable pins. SBT Input Trigger Pin: - In Key Trigger Mode, this pin is trigger pin to trigger the playback of Voice Groups one by one sequentially. - In CPU Parallel Command Mode, this pin is used as address strobe to latch the input from S1 to S4 and starts the voice playback. - In OTP Programming Mode, this pin is used as PGM signal. VDD Power Supply Pin. VSS Power Ground Pin VOUT1 and VOUT2 Digital PWM output pins which can drive speaker and buzzer directly for voice playback. OSC During voice playback, an external resistor is connected between this pin and the VDD pin to set the sampling frequency. In OTP Programming Mode, this is the ACLK input signal. VPP Connection to VDD is required during voice playback. In OTP Programming Mode, this pin is connected to a separate 6.5V power supply. OUT1, OUT2 and OUT3 - In Key Trigger Mode and CPU Parallel Command Mode, these pins are user programmable pins for the STOP pulse, BUSY and LED signals. - During OTP programming, OUT1 serves as OEB while OUT2 serves as data IO. COUT Analog 8-bit current mode D/A output for voice playback RST Chip reset in playback mode or DCLK pin in OTP programming mode.
Ver 2.2
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May 31, 2007
Integrated Circuits Inc.
VOICE SECTION COMBINATIONS
aP89021/010
Voice files created by the PC base developing system are stored in the built-in EPROM of the aP89021/010 chip as a number of fixed length Voice Blocks. Voice Blocks are then selected and grouped into Voice Groups for playback. Up to 12 Voice Groups are allowed. A Voice Block Table is used to store the information of combinations of Voice Blocks and then group them together to form Voice Group.
Chip Memory size Max no. of Voice Block No. of bytes per Voice Block Max. no. of Voice Group No. of Voice Table entries Voice Length (@ 6KHz 4-bit ADPCM) Example of Voice Block Combination
aP89021 512K bits 126 512 12 960 21 sec
AP89010 256K bits 124 256 12 960 10 sec
Assume here we have three voice files, they are "How are You?", Sound Effect and Music. Each of the voice file is divided into a number of fixed length Voice Block and stored into the memory. Voice File 1 - "How are You?" is stored in Voice Block B0 to B12. Voice File 2 - Sound Effect is stored in Voice Block B13 to B15. Voice File 3 - Music is Voice Block B16 to B40. Voice Blocks are grouped together using Voice Table to form Voice Group for playback: Group no. Group 1 Group 2 Group 3 Group 4 Voice Group contents "How are You?" Sound Effect + "How are You?" "How are You?" + Music Music Voice Table Entries B0 ... B12 B13 ... B15 + B0 ... B12 B0 ... B12 + B16 ... B40 B16 ... B40
Voice Data Compression
Voice File data is stored in the on-chip EPROM as either 4-bit ADPCM or 8-bit PCM format. Voice data stored as 4-bit ADPCM provides 2:1 data compression which can save 50% of memory space. On the other hand, voice data are stored as 8-bit PCM format means no data compression is employed but voice playback quality will be better.
Ver 2.2 5 May 31, 2007
Integrated Circuits Inc.
Programmable Options
aP89021/010
In both Key Trigger Mode and CPU Parallel Trigger Mode, user can select different trigger functions and output signals to be sent out from the pins OUT1, OUT2 and OUT3. Options affect all Voice Group playback are called Whole Chip Options. Options only affect the playback of individual Voice Group are called Group Options. Whole Chip Options * * Key or CPU Parallel Trigger Mode. Ramp-up-down enable or disable: When COUT is used for playback, Ramp-up-down should be enabled. This function eliminates the `POP' noise at the beginning and end of voice playback. When VOUT1 and VOUT2 are used to drive speaker directly, Ramp-up-down should be disabled.
Fig. 1 Ramp-up-down Enable * Output Options:
Fig.2 Ramp-up-down Disable
This option sets up the three output pins OUT1 and OUT2 to send out different signals during voice playback. Four settings are allowed: OUT1 Option 1 Option 2 LED2 STOP OUT2 LED1 LED1 OUT3 BUSY LED2
Option 3 LED1 BUSY STOP Note: Stop plus must be set to enable in order to have STOP plus to come out. The BUSY output is always HIGH during voice playback.
Fig. 3 Output waveforms
Ver 2.2
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May 31, 2007
Integrated Circuits Inc.
Group Options * * * * Edge or Level trigger Unholdable or Holdable trigger Re-triggerable or non-retriggerable Stop pulse disable or enable
aP89021/010
User selectable options that affect each individual group are called Group Options. They are:
Fig. 4 to Fig. 9 show the voice playback with different combination of triggering mode and the relationship between outputs and voice playback.
Fig. 4 Level, Unholdable, Non-retriggerable
Fig. 5 Level Holdable
Fig. 6 SBT sequential trigger with Level Holdable and Unholdable
Ver 2.2 7 May 31, 2007
Integrated Circuits Inc.
aP89021/010
Fig. 7 Edge, Unholdable, Non-retrigger
Fig. 8 Edge, Holdable
Fig. 9 SBT sequential trigger with Edge Holdable and Unholdable
Ver 2.2
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May 31, 2007
Integrated Circuits Inc.
Overlap trigger is supported with Level/Unholdable trigger options:
aP89021/010
Fig. 10 Overlap trigger
Ver 2.2
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May 31, 2007
Integrated Circuits Inc.
TRIGGER MODES
There are two triggering modes available for aP89021/010.
aP89021/010
Key or CPU Trigger modes are determined by setting the EPORM programmable options during voice data compilation. Key Trigger Mode With this trigger mode, up to 12 Voice Groups are triggered by setting S1 to S4 to HIGH or NC (not connected) in different combinations. Each Voice Group can have its only independent trigger options (See Fig. 4, 5, 7 and 8 for trigger options definition). Voice Groups can also be triggered sequentially by setting SBT pin to HIGH.
CPU Parallel Trigger Mode In this mode, S1 to S4 are set to HIGH or LOW according to the table on the following page and followed by setting the SBT input pin to HIGH, the corresponding Voice Group will be triggered. Trigger options defined in Fig. 4, 5, 7 and 8 are valid for this mode.
Fig. 11 CPU Parallel Trigger Mode Note that SBT pin cannot be used as Single Button Sequential trigger in this mode. In stead, it acts as a Strobe input to clock-in the data input from S1 to S4 into the chip.
Ver 2.2
10
May 31, 2007
Integrated Circuits Inc.
Key Trigger Mode Up to 12 Voice Groups can be triggered by S1 to S4. Voice Group 1 2 3 4 5 6 7 8 9 10 11 12 S1 HIGH NC NC NC HIGH NC NC HIGH HIGH NC HIGH HIGH S2 NC HIGH NC NC HIGH HIGH NC NC HIGH HIGH NC HIGH S3 NC NC HIGH NC NC HIGH HIGH NC HIGH HIGH HIGH NC
aP89021/010
S4 NC NC NC HIGH NC NC HIGH HIGH NC HIGH HIGH HIGH
CPU Trigger Mode Up to 12 Voice Groups can be triggered by supplying address to [S4:S1] with SBT as strobe signal. Voice Group 1 2 3 4 5 6 7 8 9 10 11 12 S4 0 0 0 0 0 0 0 0 1 1 1 1 S3 0 0 0 0 1 1 1 1 0 0 0 0 S2 0 0 1 1 0 0 1 1 0 0 1 1 S1 0 1 0 1 0 1 0 1 0 1 0 1
Ver 2.2
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May 31, 2007
Integrated Circuits Inc.
BLOCK DIAGRAM
aP89021/010
ABSOLUTE MAXIMUM RATINGS
Symbol VDD - VSS VIN VOUT T (Operating): T (Junction) T (Storage) Rating -0.5 ~ +4.5 VSS - 0.3Ver 2.2
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May 31, 2007
Integrated Circuits Inc.
Symbol Parameter
VDD ISB IOP VIH VIL IOL IOH ICO IOH IOL F/F Operating Voltage Standby current Operating current "H" Input Voltage "L" Input Voltage VOUT low O/P Current VOUT high O/P Current COUT O/P Current O/P high Current O/P low Current
aP89021/010
Unit
V A mA V V mA mA mA mA mA I/O open I/O open VDD=3.0V VDD=3.0V Vout=0.3V, VDD=3.0V Vout=2.5V, VDD=3.0V VCOUT=1.0V, VDD=3.0V VOH=2.5V, VDD=3.0V VOL=0.3V, VDD=3.0V
DC CHARACTERISTICS ( TA = 0 to 70, VDD = 3.3V, VSS = 0V )
Min.
2.2 2.5 -0.3 -5
Typ.
3.0 1 3.0 0 120 -120 -3 -8 8
Max.
3.6 5 15 3.5 0.5 +5
Condition
Frequency Stability
%
Fosc(2.7V) - Fosc(3.4V) Fosc(3V)
Ver 2.2
13
May 31, 2007
Integrated Circuits Inc.
TIMING WAVEFORMS
KEY Trigger Mode
tKD S1~S4, SBT COUT STOP BUSY tBD tBH tSTPD
aP89021/010
tSTPW
CPU Parallel Mode
Addr. S1~S4 SBT tAS tAH
tSBTW
AC CHARACTERISTICS
Symbol tKD tKD tSTPD tSTPW tBD tBH tAS tAH tSBTW tLEDC Parameter
( TA = 0 to 70, VDD = 3.3V, VSS = 0V, 8KHz sampling )
Min. 16 24 100 100 16
Typ. 64 100 3
Max. 256 100
Unit ms ms s ms ns ns ns ns ms Hz
Note 1 1
Key trigger debounce time Key trigger debounce time - retrigger STOP pulse output delay time STOP pulse width BUSY signal output delay time BUSY signal output hold time Address set-up time Address hold time SBT stroke pulse width LED flash frequency
1
1 2
Notes : 1. This parameter is inversely proportional to the sampling frequency. 2. This parameter is proportional to the sampling frequency.
Ver 2.2
14
May 31, 2007
Integrated Circuits Inc.
OSCILLATOR RESISTANCE TABLE
Sampling Frequency KHz 4.90 5.26 5.88 6.09 6.33 6.67 6.85 7.14 7.46 7.70 8.06 8.47 8.93 9.26 9.80 10.42 ROSC KOhm
300 290 280
aP89021/010
ROSC KOhm 140 130 120 110 100 91 82 75 68 62 56 51 43 Sampling Frequency KHz 11.00 11.76 12.50 13.33 14.51 15.63 16.95 18.18 19.23 20.83 22.22 23.81 25.00
270 260 250 240 230 220 210 200 190 180 170 160 150
Note: The data in the above tables are within 3% accuracy and measured at VDD = 3.0V. Oscillator frequency is subjected to IC lot to lot variation.
Ver 2.2
15
May 31, 2007
Integrated Circuits Inc.
TYPICAL APPLICATIONS
Key Trigger Mode
aP89021/010
0.1uF
C1
VDD,VPP
ROSC
8 1/4W Speaker
RST OSC COUT
Rb T
3.3V
S1 S2 S3 S4
VOUT1 VOUT2 OUT1 VSS
8 / 16 Speaker
SBT
Fig. 12 Using 3.3V Battery
HT7335
0.1uF C1 8 1/4W Speaker
VDD,VPP
ROSC
RST OSC COUT
Rb T
4.5V
S1 S2 S3 S4
VOUT1 VOUT2 OUT1 VSS
8 / 16 Speaker
SBT
Output driving of HT LDO: HT7136 (30mA, 3.6V) HT7133 (30mA, 3.3V) HT7536 (100mA, 3.6V) HT7335 (250mA, 3.5V)
Fig. 13 Using 4.5V Battery
Ver 2.2 16 May 31, 2007
Integrated Circuits Inc.
CPU Parallel Mode
aP89021/010
VIN=+5V
VOUT=+3.5V
HT7335
0.1uF ROSC C1 8 1/4W Speaker
VDD,VPP RST OSC COUT
Rb T
Addr[0] Addr[1] Addr[2] Addr[3]
Rin
S1 S2 S3 S4
Note: 1. C1 is capacitor from 0.1uF to 4.7uF depends on the kind of Vdd source and sound loudness. 2. Rb is base resistor from 120 Ohm to 390 Ohm depends on Vdd value and transistor gain. 3. T is an NPN transistor with beta larger than 150. 4. Reference value for the above components are C = 2.2uF, Rb = 390 Ohm and T = 8050D. 5. Refer to the Oscillator Resistor Table for suitable value of Rosc.
MCU
Ver 2.2
I[0..2]
3
OUT[1..3] VSS
Rin = 860K x (VIN-VOUT) / VIN
Fig. 14 5V CPU Control with COUT
17
May 31, 2007
Integrated Circuits Inc.
6. Bonding Diagram (aP89021)
aP89021/010
Bonding Diagram (AP89010)
Note: Substrate should be connected to Vss. Bonding pad size: 80um x 90um
Ver 2.2
18
May 31, 2007

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